Project dates: May 2000 – December 2001
Manpower: 120 man-months
Team Leader: Victor Vengerov, Senior Software Engineer
The task was to develop and test the firmware code for communication
processor handling all ATM-related functionality. The project included:
-
the study of the similar communication processors, including ATMizer,
Power QUICC II, other;
-
review of related standards;
-
definition of features to be implemented in the firmware
(see feature list below);
-
design of firmware architecture and data structures;
-
development of firmware functional model in ANSI C;
-
development of host driver prototype;
-
development of test suite to verify the functionality;
-
clarification of chip’s hardware architecture;
-
development of target hardware simulator (including communication
processor ISS, controllers and data path models)
-
conversion of the C model into proprietary assembler language;
-
testing the firmware on the simulator and improvement of test coverage;
-
development of performance tests; evaluation of firmware performance
using the simulator;
-
development of firmware code optimization tools;
-
additional manual code optimization to fit into size and performance
requirements,
-
verification of the code on the Verilog model of the processor;
-
testing the functionality on the real silicon;
-
creation the "ATM Firmware User’s Manual" document draft.
The project has been completed in time. Defined functionality has been
implemented in firmware completely. Firmware tests were run on actual
hardware successfully.
Firmware fit into 8K instruction words; on project completion about 200
instruction words were reserved for maintenance. ADSL performance objective
was achieved. VDSL performance achieved with restrictions
(descriptors stored in the local memory).
